1. Field of the Invention
The present invention generally relates to the control of instructions to a pipelined processor of a stored program data processing machine and, more particularly, to an apparatus for controlling the instruction dispatch, issue, execution and pipeline recovery in a microprocessor capable of executing multiple instructions out-of-order every machine clock cycle.
2. Description of the Prior Art
High performance microprocessors are relying on hardware performed dependency analysis and register renaming to facilitate the out-of-order execution of multiple instructions per machine cycle. Representative prior art in this field is the work by John Cocke et al., as described in U.S. Pat. No. 4,992,938, and the work by R. N. Rechtschaffen, as described in U.S. Pat. No. 4,574,349. In particular, Cocke et al. disclose a control mechanism for allowing parallelism among floating point operations by overlapping loads and stores with other instructions. The correct sequence of results is maintained by register renaming; that is, by removing the final assignment of architected registers to physical registers. Rechtschaffen discloses a processor complex wherein a greater number of instruction addressable hardware registers are provided in a central processing unit (CPU) than can be identified by register addressing fields of a program instruction. Rechtschaffen provides a pointer assignment mechanism which assigns unique pointer values to hardware registers, although the same general purpose register (GPR) may be identified in address fields of subsequent load instructions.